Oscillator control circuit

ABSTRACT

Servo-control loop with an outside frequency affecting an oscillator for regulating by means of the voltage (VCO) formed by logic circuits operating in a wide band and comprising a means for adjusting the phase, giving a standard phase shift throughout the band.

United States Patent [191 Bastide et al.

[111 3,872,396 [451 Mar. 18, 1975 Appl. No.: 413,350

References Cited UNITED STATES PATENTS Ball et a1 328/155 X Nordahl 1338/155 Silva et a1. 328/155 X Babany 307/233 A Zwitter et al. 307/271Widmer 331/1 A Margala et a1 331/1 A Primary Examiner.lohn S. HeymanAttorney, Agent, or Firm-Craig & Antonelli Foreign Application PriorityData 1 Nov. 6, 1972 France 72.39206 U.S.Cl. ..331/1 A, 331/17 Int. Cl.H03b 3/04 Field of Search 307/233 A; 328/155, 134; 331/1 A, 17,25

ABSTRACT Servo-control loop with an outside frequency affecting anoscillator for regulating by means of the voltage (VCO) formed by 'logic'circuits operating in a wide band and comprising a means for adjustingthe phase, giving a standard phase shift throughout the band.

I 11 Claims, 5 Drawing Figures TRANSFER L ao cfi NET/WORK Fz f1 Z1 E1 1INTERGATOR 1 00 G 2 f2 E2 Z2 TRANSFER 'li Fl NETWORK OSCILLATOROSCILLATOR CONTROL CIRCUIT The invention comes within the branch ofdevices ensuring the servo-controlling of the frequency of an oscillatorwhich may be controlled by the voltage at a frequency of a signal giventhrough a looped circuit which applies to the said oscillator anadequate control voltage, generated by a phase discriminator inserted inthe loop. It concerns a looped circuit of the above type comprisingessentially logic circuits. It is applied to the generating of aservo-controlled frequency whose phase may be varied according to auniform law in a very wide frequency band, with a view to use for thedemodulation of waves modulated by the displacement of pulses.

The invention has for its object a loop for servocontrolling thefrequency of an oscillator controlled by the voltage (f2) at an incidentfrequency (fl) comprising a simple means for making the phase of thefrequency generated vary in relation to the incident frequency,according to a uniform law in a very wide band (for example, exceeding 4octaves).

-It is a known practice to make the phase vary between two signalshaving the same frequency by inserting on one of them a delayingelement, but if the frequency varies in a ratio of to 20, as in-thepresent case, such a dephasing method is quite inadequate, for everyeffort is made to obtain the same dephasing law throughout the rangecovered. This is not the case with a uniform delay law throughout thewhole range.

of the integrator. It is immediately deduced therefrom that the saidpulse trains at the input of the logic circuit must be in quadrature,inasmuch as the input circuits have identical impedance (Z, Z 2 But ifthat identical state of impedance is altered, the compensation conditionat the inputs of the integrator corresponds to a different phaserelation between the pulse trains, hence between the incidentfrequencyjl and the generator frequency f2. A simple variable resistorinserted in one of the two input circuits produces .the condition Z, Z0,Z2 20, this causing a dephasing of the frequencyf2 in relation to theincident frequency fl, in the locking state, this dephasing beingconstant throughout the whole frequency range.

It will be observed that such a servo-control loop operates with a zeroerror signal, contrary to known servo-controlled loops which comprise aresidual error signal.

The invention has furthermore remarkable particularities.

On the one hand, it is the integrator itself, energized by thedifference between the frequencies fl and f2 which provides to theoscillator the control voltage necessary for the preliminary searchbringing the frequency f2 within the capting radius of the servocontrol.

On the otherhand, in the case where the incident fre-' quency fl happensto disappear temporarily, the logic circuit assumes a memory function,keeping for the frequency f2 the value which it had at the instant ofthe disappearance of fl. When the frequency reappears (on condition thatit has not varied appreciably), it immediately resumes its controllingfunction.

The invention will be described in detail with refer ence to theaccompanying drawings among which:

FIG. 1 is a simplified block diagram of a device according to theinvention;

FIG. 2 is a general diagram;

FIG. 3 is a set of graphs helping in understanding the I operation;

FIG. 4 shows curves illustrating the operation; and 5 FIG. 5 shows thedevelopment of the locking process as a function of time.

In FIG. 1 the assembly comprises a logic circuit L,

which receives, through a terminal 1, currents having an incidentfrequency fl andthrough a terminal 2, currents. having a frequency]?generated in the device supplies to two complementary terminals Q Q,,,complementary rectangular signals. These signals pass through thetransfer impedances Z1, Z2 (Z1 adjustable), respectively, and reach theinputs El, E2 of the integrator G having two inputs, whose voltageoutput voltage (arrow F1) controls an oscillator P controlled by avoltage. When the locking between the frequencies f1 and f2 is not yetes-' tablished or is cut off, the logic circuit L sends to theintegrator a resetting to zero signal (arrow F2). The integrator G thenpositions the oscillator at itsmaximum frequency (for example, 400kc/s), then, receiving, at its terminals El, E2, the signals coming fromthe difference between the frequencies fl and f2 applied to the logiccircuit L, applies to the oscillator G a control voltage (negative)whose intensity increases until the arrival at equality of thefrequencies fl i-"j2, this corresponding to a constant voltage at theoutput of the integrator G.

In FIG. 2 the incident signal whose frequency is f1 comes in through aterminal 1, passes through a frequency divider 3 dividing by N and adifferentiator circuit 4 which provides fine pulses having a frequencyof fl/N. The advantage of that frequency division will be seenherebelow.

The output frequencyj2 is supplied to a terminal 2. It also passesthrough a frequency divider 5 dividing by N and a differentiator circuit6.

That frequency is generated by a variable frequency oscillator Pcomprising two monostable multivibra'tors M1, M2, in reciprocalreaction. The first has a time constant determined by two components, C1and R1. The second has a time constant determined by a capacity C2 and anetwork of two resistors R2, R'2, the latter being shunted by a fieldeffect transistor T0, whose internal resistance is regulated by acontinuous variable voltage.

By a variation in the regulating voltage applied to the field effecttransistor T0, such a circuit may cover a frequency band in a ratiogreater than 10, for example, in a particular case of application, from20 to 400 kc/s.

The logic circuit L comprises four bistableflip-flops Y0, Y1, Y2, Y3 andan AND gate 7. The bistable flipflops are all of the same type the JKmaster-slave flip-flop. They have a clock input H, an input reset tozero, called a clear input", designated here by Z, and input 1, an inputK, two inputs Oi, Oi, i designating the index peculiar to a flip-flop(Yo, Y 1, Y2, Y3), on the flip-flops Y1, Y2, Y3 the outputs Q is notused.

The flip-flop Yo fulfills the function of a phase discriminator. Theterminal Z of Y is connected up to the output of the differentiator 4;its terminal H is connected up to the output of the differentiator 6.Its terminal J is at the logic level 1, the terminal K is connected upto the output Q3 of the flip-flop Y3 (see herebelow). Its outputterminals Q0,Q are connected up to the inputs E1, E2 of the inputcircuit of an amplifier A0 connected up as an integrator, through twotransfer networks Z1, Z2.

Three flip-flops Y1, Y2, Y3 form a detector circuit for detecting theexceeding of the frequency. Their connections are the following:

J K M 2 Q Y1 l 1 output 4 output 6 H of Y2 Y2 l 1 01 output 6 H of Y3(input 7) Y3 l 0 Q2 output 7 (terminal K of Y0) (input Al) fd Referencenumeral 7 is an AND gate having three inputsv acting a a detector ofcoincidence between the pulses leaving 4 and the pulses leaving 6. Theoutput of 7 is validated by the output signal of Q3. If Q3 is at 1, acoincidence pulse coming from 7 could be applied to the control input ofa monostable multivibrator resistor R10.

The monostable multivibrator M0 may also be tripped by a manualoperation earthing by the knob 9. The output signal of the monostablemultivibrator M0 is applied through an amplifier A2 controlling theconductivity to a field effect transistor T3 operating as a switch.

A differential amplifier A0 having two inputs E1, E2 and has an inputcircuit with two transfer networks. The first impedance transfer networkZl, connected up at O0, comprises a variable resistor R3 in series, aresistor R5 in parallel and, in series, two resistors R7, R'7 inparallel, the latter being in series with a field effect transistor T1.The second impedance transfer network Z2 connected up at m comprises aseries resistor R4, a parallel resistor R6 and, in series, two resistorsR8, R8 in parallel, the latter being in series with a field effecttransistor T2 and lastly, a capacitor in C4 in parallel, whose functionis to supply a time constant to the second transfer network.

The amplifier A0 is equipped as an integrator by a negative reactioncircuit comprising a parallel network R9, C3 and a capacitor Co, whichis shunted by a field effect transistor T3. The circuit output voltageof the integrator G is applied through F l to the grid terminal of thefield effect transistor T0.

The field effect transistor T0 acts through its variable resistor on thefrequency f2 supplied by the oscillator The field effect transistorsTl,'T2, energized by an amplifier Al, connecting or cuttingsimultaneously the resistors R'7, R8 respectively, supply to theintegrator a short or long time constant.

The short time constant (relatively wide pass band) corresponds to thelocking frequency search process. The long time constant (narrower passband) corresponds to the locking state, which is all the less subject tothe interference as the pass band of the servo control loop is narrower.

The field effect transistor T3 is put into a shortcircuit state throughan amplifier A2 (through F2) by the tripping of the monostablemultivibrator M0. In these conditions, it discharges the capacitor C0 ofthe integrator A0, this having the effect of bringing the frequencyjZ tothe maximum value. It will beshown herebelow that the charge accumulatedon thecapacitor C0 and the output voltage increase through the operationof the integrator during the search phase, this having the effect ofreducing the frequency/2 until the locking on the frequency f1 of theincident signal. Atthat instant, the voltage on C0-becomes stabilized,as does the output voltage. Y

The monostable multivibrator M0 is tripped either by manual control(knob 9) or automatically on an unlocking operation (output of 7) Theamplifiers A1 and A2 do not, actually speaking, operate as amplifiers.Their function is to supply an alignment of a signal from one continuouslevel to an-- Graph a shows the positive pulses having a frequency fl/Nreaching the terminal H of Y1.

Graph b shows the negative pulses having a fre:

quencyj2/N reaching the terminal Z of Y1 andthe terminal Z or Y2.

Graph c shows the signals on Q1.

Graph d shows the signals on Q2.

Graph e shows the signals on Q3.

Graph fshows the signals on Q0.

Graph g shows the signals on Q0 in the particular case where, afterlocking, the incident signal is canceled.

At the beginning of a search, there are many more pulses b than pulsesa. After a pulse a, which sets O1 to l, a pulse b, which brings back Q1to 0 (graph 0), ar-

rives.

At the end of each stage of Q1, Y2 receives at H a controllingdescending wave front. But the effect of that pulse is canceled by thepulse b simultaneously reaching Z of Y2. Q2 remains at zero (graph d)which has the priority by construction of the bistable flip-flop.

The result of this. on Q0 (graph f) is a factor having a very differentform from the ratio 1/ i, when a variable voltage is applied to thefield effect transistor To, this reducing the frequency f2/N.

At the instant to, the frequency f2/N has decreased sufficiently foranother pulse a, having an order of x l to arrive after a pulse 0 havingan order of xbefore a pulse b. The descending wave front ofQl sets theterminal Q2 of Y2 to 1, this falling back to zero on the pulse b whichfollows.

That temporary pulse reaching H of Q3 makes 03 change over to lpermanently (graph e).

The changing over of O3 to 1 has the following consequences:

l. The coincident pulses which were inhibited up till now at the outputof the gate 7 have a free passage towards the monostable multivibratorM0. This happens when, after a locking operation, unlocking occurs,this, bringing about a difference in the frequencies, makes coincidencesappear rapidly.

The coincidences which occur during the search phase have no effect onM0, for they are blocked by the Q3 applied to the gate 7.

2. The terminal K of Y0, which was at zero, changes over to 1. In thelocking state, no consequence in the operation of Y0 results therefrom.

3. The field effect transistors T1 and T2, which were conductive, havinga negligible internal resistance, are cut off. The time constant ofintegration becomes longer,

Graph fshows that the factor having the form of the signal at Q0, whichwas very different from 1/1, becomes equal to 1/] when the locking iseffective, a fraction of a millisecond after to. If the circuits Z1 andZ2 are adjusted to the same value of impedance Z1 Z2, the pulses b areexactly in the middle of the gap between two pulses a. That state ismaintained during the whole of the locking period. There is therefore nocoincidence pulse at the output of 7 as long as the locking ismaintained.

If the condition Z1 Z2 is not fulfilled, the pulses of one train areshifted in relation to the middle of the gap of the other train.

The locking is maintained even if the frequency f happens to vary, oncondition that the variation be fairly slow.

If the signal having a frequency of f1 happens to disappear, thechangeover to l of the terminal K of Y0 ensures the tilting thereof oneach pulse reaching H. The result thereof on Q0 (and on (Y), of course)is a signal having half the frequency (graph g) of the preceding case(graph j). But as the form factor is still 1/], there is no disturbanceat the output of the integrator the frequency f2 is preserved. If, onthe reappearance of the signal, its frequency fl has not varied verymuch, the servo-controlling is preserved. That memory function preservesthe frequency well, but does not preserve the phase.

FIG. 4 shows the action of the variation of the resis-- tor R3 (FIG. 2)on the adjusting of the phase of the wave having a frequency of F2 inrelation to the wave having a frequency offl.

FIG. 4 comprises four graphs grouped into complementary signals, p,p',and q, q at inputs E E respectively. It is assumed, for example, thatthe duration of a complete period covers 10 arbitrary units.

The graphs p, p' correspond to the case Z1 Z2. The gating pulses p and phave the same amplitude V (for example, V 3 arbitrary units) and afactor having the form 1/1. The average v is equal to half of v for thegating pulses p and for the gating pulses p. The positive gating pulsesp and p have the same width a, for example, u 5 arbitrary units.

It is assumed that the variable resistance R3 is modified. The result ofthis is that Z1 9* Z2. Graph q shows that the gating pulses affected bythe variation of R3 have, for example, an amplitude V 2, whereas thegating pulses q retain their amplitude V 3. The balance which isreestablished compulsorily (since the frequency has not changed)requires that the new average v of the gating pulses q be equal to thenew average of the gating pulses q. An elementary calculation shows thatthe positive gating pulses q assume the width a 6 and that the positivegating pulses q assume the complementary width 10 6 4.

That deviation of the factor of form of the rectangular signalsreflects, according to an exactly rectilinear law, a dephasing betweenthe pulse trains having a frequency offl and f2. The treating of thepulses being ef-' FIG. 3

The'curve 1 shows the variation for an adjustment at the top of therange (for example, 300 kc/s), the curve 2 for an adjustment at thebottom of the range (24 kc/s).

The slope is relatively great at the outset and reduces, progressively,to cancel out at the arrival at the instant to of the locking. Thatcharacteristic which constitutes an advantage and procures progressiveand hence reliable locking conditions, is supplied by the intrinsic constitution of the device.

The device and the operation thereof have been described in the ase ofan interconnection between the terminals Q0, Q0 and the input terminalsE1, E2 of the integrator.

Nevertheless, the same results may be attained for a single connection,for example between Q0 and E, E2 being connected up to a continuoussource. In that case, dephasing will be obtained by modifying the valueof the continuous voltage applied to the input E2.

But the use of the two complementary signals Q0, Q 0

is a greater advantage, for it ensures the compensating of certaindrifts, more particularly, thermal drifts.

What is claimed is:

1. A control circuit for servo-controlling the frequency generated by acontrol oscillator in accordance with the frequency of a control signal,said circuit providing a phase-adjustable frequency control loop andcomprising logic circuit means connected to receive said control signaland the output of said control oscillator for providing first and secondrectangular complementary signals on respective outputs, an integratorcircuit, and first and second transfer networks connecting therespective outputs of said logic circuit means to said integratorcircuit, the output of said integrator circuit being connected incontrol of the frequency of said control oscillator, one of said firstand second transfer networks having a variable impedance.

2. A control circuit as defined in claim 1 wherein said logic circuitmeans includes means connected to said integrator circuit for settingsaid integrator circuit to zero.

3. A control circuit for servo-controlling the frequency generated by acontrol oscillator in accordance with the frequency of a control signalcomprising logic circuit means connected to receive said control signaland the output of said control oscillator for providing first and secondrectangular complementary signals on respective outputs, and integratorcircuit, and first and second transfer networks connecting therespective outputs of said logic circuit means to said integratorcircuit, the output of said integrator circuit being connected incontrol of the frequency of said control oscillator, one of said firstand second transfer networks having a variable impedance, wherein saidlogic circuit means includes first and second frequency dividers bratorsconnected in reciprocal reaction, characterized in that one of themonostable multivibrators is equipped with a first field effecttransistor operating as a variable resistor, receiving on its controlelectrode the output of integrator circuit.

5. A control circuit as defined in claim 3 wherein said integratorcircuit includes an integrator-amplifier having first and second inputterminals connected to said first and second transfer networks and afeedback circuit including a capacitor.

6. A control circuit as defined in claim 5 wherein said logic circuitmeans further includes a first logic subassembly which is responsive tothe outputs of said first and second differentiators for providing afirst output when the output frequency of said control oscillatorsubstantially equals the frequency of said control signal and a secondoutput when these frequencies substantially differ.

7. A control circuit as defined in claim 6 wherein said logic circuitmeans further includes means responsive to the outputs of said firstlogic subassembly for controlling the impedance of said first and secondtransfer networks.

8. A control circuit as defined in claim 7 wherein said logic circuitmeans further includes a second logic subassembly connected to theoutputs of said first and second differentiators and said first logicsubassembly for resetting said integrator-amplifier to zero when saidfirst logic subassembly provides said second output.

9. A control circuit as defined in claim 2 wherein said means forresetting said integrator-amplifier to zero includes a second fieldeffect transistor connected in parallel to said capacitor and operatingas a switch.

10. A control circuit as defined in claim 6 wherein when said firstlogic subassembly provides said second output, said phase discriminatoroperates as a divider by two of the frequency at the output of saidsecond differentiator in the case of disappearance of the frequency atthe output of said first differentiator.

11. A control circuit for servo-controlling the frequency generated by acontrol oscillator in accordance with the frequency of a control signal,said circuit comprising a phase-adjustable frequency control loopincluding logic circuit means connected to receive said control signaland the output of said control oscillator for providing first and secondcomplementary signals on respective outputs, an integrator circuit forcontrolling the frequency generated by said control oscillator, firstand second transfer networks connecting the respective outputs of saidlogic circuit means to said inte- I equal to the frequency of saidcontrol signal.

1. A control circuit for servo-controlling the frequency generated by acontrol oscillator in accordance with the frequency of a control signal,said circuit providing a phaseadjustable frequency control loop andcomprising logic circuit means connected to receive said control signaland the output of said control oscillator for providing first and secondrectangular complementary signals on respective outputs, an integratorcircuit, and first and second transfer networks connecting therespective outputs of said logic circuit means to said integratorcircuit, the output of said integrator circuit being connected incontrol of the frequency of said control oscillator, one of said firstand second transfer networks having a variable impedance.
 2. A controlcircuit as defined in claim 1 wherein said logic circuit means includesmeans connected to said integrator circuit for setting said integratorcircuit to zero.
 3. A control circuit for servo-controlling thefrequency generated by a control oscillator in accordance with thefrequency of a control signal comprising logic circuit means connectedto receive said control signal and the output of said control oscillatorfor providing first and second rectangular complementary signals onrespective outputs, and integrator circuit, and first and secondtransfer networks connecting the respective outputs of said logiccircuit means to said integrator circuit, the output of said integratorcircuit being connected in control of the frequency of said controloscillator, one of said first and second transfer networks having avariable impedance, wherein said logic circuit means includes first andsecond frequency dividers connected to receive said control signal andthe output of said control oscillator, respectively, first and seconddifferentiators connected to the outputs of said first and secondfrequency dividers, and a phase discriminator having first and secondinputs connected to said first and second differentiators and first andsecond outputs connected to said first and second transfer networks. 4.A control circuit as defined in claim 3 wherein said control oscillatorcomprises two monostable multivibrators connected in reciprocalreaction, characterized in that one of the monostable multivibrators isequipped with a first field effect transistor operating as a variableresistor, receiving on its control electrode the output of integratorcircuit.
 5. A control circuit as defined in claim 3 wherein saidintegrator circuit includes an integrator-amplifier having first andsecond input terminals connected to said first and second transfernetworks and a feedback circuit including a capacitor.
 6. A controlcircuit as defined in claim 5 wherein said logic circuit means furtherincludes a first logic subassembly which is responsive to the outputs ofsaid first and second differentiators for providing a first output whenthe output frequency of said control oscillator substantially equals thefrequency of said control signal and a second output when thesefrequencies substantially differ.
 7. A control circuit as defined inclaim 6 wherein said logic circuit means further includes meansresponsive to the outputs of said first logic subassembly forcontrolling the impedance of said first and second transfer networks. 8.A control ciRcuit as defined in claim 7 wherein said logic circuit meansfurther includes a second logic subassembly connected to the outputs ofsaid first and second differentiators and said first logic subassemblyfor resetting said integrator-amplifier to zero when said first logicsubassembly provides said second output.
 9. A control circuit as definedin claim 2 wherein said means for resetting said integrator-amplifier tozero includes a second field effect transistor connected in parallel tosaid capacitor and operating as a switch.
 10. A control circuit asdefined in claim 6 wherein when said first logic subassembly providessaid second output, said phase discriminator operates as a divider bytwo of the frequency at the output of said second differentiator in thecase of disappearance of the frequency at the output of said firstdifferentiator.
 11. A control circuit for servo-controlling thefrequency generated by a control oscillator in accordance with thefrequency of a control signal, said circuit comprising aphase-adjustable frequency control loop including logic circuit meansconnected to receive said control signal and the output of said controloscillator for providing first and second complementary signals onrespective outputs, an integrator circuit for controlling the frequencygenerated by said control oscillator, first and second transfer networksconnecting the respective outputs of said logic circuit means to saidintegrator circuit, one of said first and second transfer networkshaving a variable impedance, said logic circuit means including afrequency overshoot detection circuit for detecting when the frequencygenerated by said control oscillator differs from the frequency of saidcontrol signal, an initialization circuit responsive to said frequencyovershoot detection circuit for setting said integrator circuit to zero,and a locking control circuit responsive to said frequency overshootdetection circuit for effecting a phase locking operation when thefrequency generated by said control oscillator becomes equal to thefrequency of said control signal.